/*
 * Copyright (c) 2013, Freescale Semiconductor, Inc.
 * All rights reserved.
 *
 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 * OF SUCH DAMAGE.
 */
/*
 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
 *
 * This file was generated automatically and any changes may be lost.
 */
 
#include "gpio_map.h"
#include "registers/regsiomuxc.h"

// First subscript is bank, second is pin within the bank. There are always 32 pin
// entries per bank. If a pin does not have an assigned GPIO, its address is 0.
const uint32_t k_gpio_mux_registers[HW_GPIO_INSTANCE_COUNT][GPIO_PIN_COUNT] =
    {
        // Bank 1
        {
            HW_IOMUXC_SW_MUX_CTL_PAD_AUD_RXFS_ADDR, // Pin 0
            HW_IOMUXC_SW_MUX_CTL_PAD_AUD_RXC_ADDR, // Pin 1
            HW_IOMUXC_SW_MUX_CTL_PAD_AUD_RXD_ADDR, // Pin 2
            HW_IOMUXC_SW_MUX_CTL_PAD_AUD_TXC_ADDR, // Pin 3
            HW_IOMUXC_SW_MUX_CTL_PAD_AUD_TXFS_ADDR, // Pin 4
            HW_IOMUXC_SW_MUX_CTL_PAD_AUD_TXD_ADDR, // Pin 5
            HW_IOMUXC_SW_MUX_CTL_PAD_AUD_MCLK_ADDR, // Pin 6
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_ADDR, // Pin 7
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_ADDR, // Pin 8
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_ADDR, // Pin 9
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_ADDR, // Pin 10
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_ADDR, // Pin 11
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_ADDR, // Pin 12
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_ADDR, // Pin 13
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_ADDR, // Pin 14
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_ADDR, // Pin 15
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_ADDR, // Pin 16
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_ADDR, // Pin 17
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_ADDR, // Pin 18
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_ADDR, // Pin 19
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_ADDR, // Pin 20
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_ADDR, // Pin 21
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_ADDR, // Pin 22
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_ADDR, // Pin 23
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_ADDR, // Pin 24
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_ADDR, // Pin 25
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_ADDR, // Pin 26
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_ADDR, // Pin 27
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_ADDR, // Pin 28
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_ADDR, // Pin 29
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_ADDR, // Pin 30
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_ADDR, // Pin 31
        },
        // Bank 2
        {
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_ADDR, // Pin 0
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_ADDR, // Pin 1
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_ADDR, // Pin 2
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_VCOM0_ADDR, // Pin 3
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_VCOM1_ADDR, // Pin 4
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_ADDR, // Pin 5
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_ADDR, // Pin 6
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_CTRL0_ADDR, // Pin 7
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_CTRL1_ADDR, // Pin 8
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_CTRL2_ADDR, // Pin 9
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_CTRL3_ADDR, // Pin 10
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_ADDR, // Pin 11
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_IRQ_ADDR, // Pin 12
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_ADDR, // Pin 13
            HW_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_WAKE_ADDR, // Pin 14
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_ADDR, // Pin 15
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_ADDR, // Pin 16
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_ADDR, // Pin 17
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_ADDR, // Pin 18
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_ADDR, // Pin 19
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_ADDR, // Pin 20
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_ADDR, // Pin 21
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_ADDR, // Pin 22
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_ADDR, // Pin 23
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_ADDR, // Pin 24
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_ADDR, // Pin 25
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_ADDR, // Pin 26
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_ADDR, // Pin 27
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_ADDR, // Pin 28
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_ADDR, // Pin 29
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_ADDR, // Pin 30
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_ADDR, // Pin 31
        },
        // Bank 3
        {
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_ADDR, // Pin 0
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_ADDR, // Pin 1
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_ADDR, // Pin 2
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_ADDR, // Pin 3
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_ADDR, // Pin 4
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_ADDR, // Pin 5
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_ADDR, // Pin 6
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_ADDR, // Pin 7
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_ADDR, // Pin 8
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_ADDR, // Pin 9
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_ADDR, // Pin 10
            HW_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_ADDR, // Pin 11
            HW_IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_ADDR, // Pin 12
            HW_IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_ADDR, // Pin 13
            HW_IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_ADDR, // Pin 14
            HW_IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_ADDR, // Pin 15
            HW_IOMUXC_SW_MUX_CTL_PAD_UART1_RXD_ADDR, // Pin 16
            HW_IOMUXC_SW_MUX_CTL_PAD_UART1_TXD_ADDR, // Pin 17
            HW_IOMUXC_SW_MUX_CTL_PAD_WDOG_B_ADDR, // Pin 18
            HW_IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_ADDR, // Pin 19
            HW_IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_ADDR, // Pin 20
            HW_IOMUXC_SW_MUX_CTL_PAD_REF_CLK_24M_ADDR, // Pin 21
            HW_IOMUXC_SW_MUX_CTL_PAD_REF_CLK_32K_ADDR, // Pin 22
            HW_IOMUXC_SW_MUX_CTL_PAD_PWM1_ADDR, // Pin 23
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_ADDR, // Pin 24
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_ADDR, // Pin 25
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_ADDR, // Pin 26
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_ADDR, // Pin 27
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_ADDR, // Pin 28
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_ADDR, // Pin 29
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_ADDR, // Pin 30
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_ADDR, // Pin 31
        },
        // Bank 4
        {
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_ADDR, // Pin 0
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_ADDR, // Pin 1
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL5_ADDR, // Pin 2
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW5_ADDR, // Pin 3
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL6_ADDR, // Pin 4
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW6_ADDR, // Pin 5
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL7_ADDR, // Pin 6
            HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW7_ADDR, // Pin 7
            HW_IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ADDR, // Pin 8
            HW_IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ADDR, // Pin 9
            HW_IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_ADDR, // Pin 10
            HW_IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_ADDR, // Pin 11
            HW_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_ADDR, // Pin 12
            HW_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_ADDR, // Pin 13
            HW_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_ADDR, // Pin 14
            HW_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_ADDR, // Pin 15
            HW_IOMUXC_SW_MUX_CTL_PAD_FEC_TX_DATA1_ADDR, // Pin 16
            HW_IOMUXC_SW_MUX_CTL_PAD_FEC_RX_DATA0_ADDR, // Pin 17
            HW_IOMUXC_SW_MUX_CTL_PAD_FEC_RX_DATA1_ADDR, // Pin 18
            HW_IOMUXC_SW_MUX_CTL_PAD_FEC_RX_ER_ADDR, // Pin 19
            HW_IOMUXC_SW_MUX_CTL_PAD_FEC_MDIO_ADDR, // Pin 20
            HW_IOMUXC_SW_MUX_CTL_PAD_FEC_TX_CLK_ADDR, // Pin 21
            HW_IOMUXC_SW_MUX_CTL_PAD_FEC_TX_EN_ADDR, // Pin 22
            HW_IOMUXC_SW_MUX_CTL_PAD_FEC_MDC_ADDR, // Pin 23
            HW_IOMUXC_SW_MUX_CTL_PAD_FEC_TX_DATA0_ADDR, // Pin 24
            HW_IOMUXC_SW_MUX_CTL_PAD_FEC_CRS_DV_ADDR, // Pin 25
            HW_IOMUXC_SW_MUX_CTL_PAD_FEC_REF_CLK_ADDR, // Pin 26
            HW_IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_ADDR, // Pin 27
            HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_ADDR, // Pin 28
            HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA6_ADDR, // Pin 29
            HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_ADDR, // Pin 30
            HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA5_ADDR, // Pin 31
        },
        // Bank 5
        {
            HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA7_ADDR, // Pin 0
            HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_ADDR, // Pin 1
            HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA4_ADDR, // Pin 2
            HW_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_ADDR, // Pin 3
            HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_ADDR, // Pin 4
            HW_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_ADDR, // Pin 5
            HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_ADDR, // Pin 6
            HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA6_ADDR, // Pin 7
            HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_ADDR, // Pin 8
            HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA5_ADDR, // Pin 9
            HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA7_ADDR, // Pin 10
            HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_ADDR, // Pin 11
            HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA4_ADDR, // Pin 12
            HW_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_ADDR, // Pin 13
            HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_ADDR, // Pin 14
            HW_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_ADDR, // Pin 15
            HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_ADDR, // Pin 16
            HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_ADDR, // Pin 17
            HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_ADDR, // Pin 18
            HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_ADDR, // Pin 19
            HW_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_ADDR, // Pin 20
            HW_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_ADDR, // Pin 21
            0, // Unassigned GPIO pin 22
            0, // Unassigned GPIO pin 23
            0, // Unassigned GPIO pin 24
            0, // Unassigned GPIO pin 25
            0, // Unassigned GPIO pin 26
            0, // Unassigned GPIO pin 27
            0, // Unassigned GPIO pin 28
            0, // Unassigned GPIO pin 29
            0, // Unassigned GPIO pin 30
            0, // Unassigned GPIO pin 31
        },
    };

// v1/121109/1.2.3
// EOF
